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XRD54L08/L10/L12
May 2000-2
3V, Low Power, Voltage Output Serial 8/10/12-Bit DAC Family
FEATURES D 8/10/12-Bit Resolution D Operates from a Single 3V Supply D Buffered Voltage Output: 13ms Typical Settling Time D 145mW Total Power Consumption (typ) D Guaranteed Monotonic Over Temperature D Flexible Output Range: 0V to VDD D 8 Lead SOIC and PDIP Package D Power On Reset D Serial Data Output for Daisy Chaining
APPLICATIONS D Digital Calibration D Battery Operated Instruments D Remote Industrial Devices D Cellular Telephones D Motion Control D VXCO Control D Comparator Level Setting
GENERAL DESCRIPTION The XRD54L08/L10/L12 are low power, voltage output digital-to-analog converters (DAC) for +3V power supply operation. The parts draw only 50mA of quiescent current and are available in both an 8-lead PDIP and SOIC package. The XRD54L08/L10/L12 have a 3 wire serial port with an
output allowing the user to daisy chain several of them together. The serial port will support both Microwiret, SPIt, and QSPIt standards. The outputs of the XRD54L08/L10/L12 are set at a gain of +2. The output short circuit current is 7mA typical.
ORDERING INFORMATION
Part No. XRD54L08AID XRD54L08AIP XRD54L10AID XRD54L10AIP XRD54L12AID XRD54L12AIP Package 8 Lead 150 Mil JEDEC SOIC 8 Lead 300 Mil PDIP 8 Lead 150 Mil JEDEC SOIC 8 Lead 300 Mil PDIP 8 Lead 150 Mil JEDEC SOIC 8 Lead 300 Mil PDIP Operating Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Rev. 1.30
E2000
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z (510) 668-7017
XRD54L08/L10/L12
BLOCK DIAGRAM
VREFIN 2n Switch Matrix R
+ R VDD
VOUT
AGND
VDD
CS SCLK SDIN
Shift Register Power On Reset
DOUT
Figure 1. Block Diagram
PIN CONFIGURATION
SDIN SCLK CS DOUT
1 2 3 4
8 7 6 5
VDD VOUT VREFIN AGND
SDIN SCLK CS DOUT
1 2 3 4
8 7 6 5
VDD VOUT VREFIN AGND
8 Lead SOIC (Jedec, 0.150")
8 Lead PDIP (0.300")
PIN DESCRIPTION
Pin # 1 2 3 4 5 6 7 8 Rev. 1.30 2 Symbol SDIN SCLK CS DOUT AGND VREFIN VOUT VDD Description Serial Data Input Serial Data Clock Chip Select (Active High) Serial Data Output Analog Ground Voltage Reference Input DAC Output Supply Voltage
XRD54L08/L10/L12
Test Conditions: VDD= 3V, GND= 0V, REFIN= 1.000V (External), RL= 10kW, CL= 100pF, TA= TMIN to TMAX, Unless Otherwise Noted.
Symbol N INL DNL VOS TCVOS PSRR GE TCGE PSRR Parameter Resolution Relative Accuracy Differential Nonlinearity Offset Error Offset Tempco Offset-Error Power-Supply Rejection Ratio Gain Error Gain-Error Tempco Power-Supply Rejection Ratio Resolution Relative Accuracy Differential Nonlinearity Offset Error Offset Tempco Offset-Error Power-Supply Rejection Ratio Gain Error Gain-Error Tempco Power-Supply Rejection Ratio Resolution Relative Accuracy Differential Nonlinearity Offset Error Offset Tempco Offset-Error Power-Supply Rejection Ratio Gain Error Gain-Error Tempco Power-Supply Rejection Ratio 0 12 2 0.5 3 2 1.0 0.1 10 0.1 1.25 1.25 0.4 4 -1 1.25 VOS TCVOS PSRR GE TCGE PSRR 8 0 10 0.5 0.50 3 2 0.5 0.1 10 0.1 1.25 1 0.4 1 0.75 8 0 Min. 8 0.25 0.25 3 2 0.5 0.1 10 0.1 1.25 1 0.4 0.5 0.5 8 Typ. Max. Unit Bits LSB LSB mV ppm/C mV %FS ppm/C mV 2.5V VDD 3.5V, Measured at FS 2.5V VDD 3.5V Guaranteed Monotonic Conditions
ELECTRICAL CHARACTERISTICS
Static Performance XRD54L08
Static Performance XRD54L10 N INL DNL VOS TCVOS PSRR GE TCGE PSRR Bits LSB LSB mV ppm/C mV %FS ppm/C mV 2.5V VDD 3.5V, Measured at FS 2.5V VDD 3.5V Guaranteed Monotonic
Static Performance XRD54L12 N INL DNL Bits LSB LSB LSB mV ppm/C mV %FS ppm/C mV 2.5V VDD 3.5V, Measured at FS 2.5V VDD 3.5V Guaranteed Monotonic
Rev. 1.30 3
XRD54L08/L10/L12
ELECTRICAL CHARACTERISTICS (CONT'D) Test Conditions: VDD= 3V, GND= 0V, REFIN= 1.000V (External), RL= 10kW, CL= 100pF, TA= TMIN to TMAX, Unless Otherwise Noted.
Symbol VO VREG +ISC -ISC VREFIN RIN TCRIN CIN ACFT VIH VIL IIN CIN VOH VOL SR ts DFT SINAD Parameter Output Voltage Range Output Load Regulation Short-Circuit Current, Sink Short-Circuit Current, Source Voltage Range Input Resistance Input Resistance Tempco Input Capacitance AC Feedthrough Input High Input Low Input Current Input Capacitance Output High Output Low Voltage-Output Slew Rate Voltage-Output Settling Time Digital Feedthrough Signal-to-Noise Plus Distortion 0.13 0.21 13 1 68 15 VDD-1 0.4 10 2.0 0.8 1 0 40 65 1500 32 -80 40 Min. 0 2 11 2.5 VDD Typ. Max.
VDD--0.4
Unit V mV mA mA V kW ppm/C pF dB V V mA pF V V V/ms ms nV-s dB
Conditions
Voltage Output (VOUT) XRD54L08/L10/L12 4 VOUT = 2V, RL=2kW VOUT = VDD VOUT = GND Output Swing Limited, Not Code Dependent
Voltage Reference Input (VREFIN) XRD54L08/L10/L12
Not Code Dependent REFIN = 1kHz, 2Vp-p, SDIN=000h
Digital Inputs (SDIN, SCLK, CS) XRD54L08/L10/L12
VIN=0V or VDD
Digital Output (DOUT) XRD54L08/L10/L12 ISOURCE=4mA ISINK=4mA TA=+25C 1/2LSB, VOUT=2V CS=VDD, SDIN=SCLK=100kHz VREFIN=1kHz, 2Vp-p F.S., SDIN=Full Scale --3dB BW=250kHz
Dynamic Performance XRD54L08/L10/L12
Power Supply XRD54L08/L10/L12 VDD IDD Positive Supply Voltage Power Supply Current 2.5 35 3.5 60 V mA All Inputs=0V or VDD, Output=No Load, VO=0V, IREF Not Included
Switching Characteristics XRD54L08/L10/L12 tCSS tCSH0 tCSH1 CS Setup Time SCLK Fall to CS Fall Hold Time SCLK Fall to CS Rise Hold TIme 10 5 0 20 ns ns ns
Notes: 1 Total supply current consumption = I DD + IREF + (VOUT / 70K.) Rev. 1.30 4
XRD54L08/L10/L12
ELECTRICAL CHARACTERISTICS (CONT'D) Test Conditions: VDD= 3V, GND= 0V, REFIN= 1.000V (External), RL= 10kW, CL= 100pF, TA= TMIN to TMAX, Unless Otherwise Noted.
Symbol tCH tCL tDS tDH tDO tCSW tCS1 Parameter SCLK High Width SCLK Low Width DIN Setup Time DIN Hold Time DOUT Valid Propagation Delay CS High Pulse Width CS Rise to SCLK Rise Setup Time 20 10 Min. 20 20 10 0 8 40 20 15 Typ. 35 35 45 Max. Unit ns ns ns ns ns ns ns CL= 50pF Conditions
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V, +5V Digital Input Voltage to GND . . . . . . -0.3V, VDD +0.3V VREFIN . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V, VDD +0.3V VOUT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD, GND Continuous Current, Any Pin . . . . . . . . -20mA, +20mA Package Power Dissipation Ratings (TA= +70C) PDIP (derate 9mW/C above +70C) . . . . 117mW SOIC (derate 6mW/C above +70C) . . . 155mW Operating Temperature Range . . . . . -40C to + 85C Storage Temperature Range . . . . . . -65C to +165C Lead Temperature (soldering, 10 sec) . . . . . . +300C
Notes 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100ms.
Rev. 1.30 5
XRD54L08/L10/L12
TIMING
CS tCSH0 tCSW tCSS tCH tCL tCSH1
SCLK tDS SDIN tD0 DOUT tDH tCS1
Figure 2. Timing Diagram
Input 1111 1000 1000 0111 0000 0000 1111 0001 0000 1111 0001 0000 (0000) (0000) (0000) (0000) (0000) (0000)
Output + 2 (VREFIN) 255 256 + 2 (VREFIN) 129 256 + 2 (VREFIN) 128 = + VREFIN 256 + 2 (VREFIN) 127 256 + 2 (VREFIN) 1 256 0V
Note: Write 8-bit data words with four sub-LSB 0s because the DAC input latch is 12 bits wide.
Table 1. Binary Code Table
Rev. 1.30 6
XRD54L08/L10/L12
THEORY OF OPERATION XRD54L08/L10/L12 Description The XRD54L08/L10/L12 are micro-power, voltage output, serial daisy-chain programmable DACs operating from a single 3V power supply. The DACs are built on a 0.6 micron CMOS process. The features of these DACs make it well suited for industrial control, low distortion audio, battery operated devices and cost sensitive designs that want to minimize pin count on ICs. Resistor String DAC A resistor string architecture converts digital data using a switch matrix to an analog signal as shown in Figure 3.
VREFIN 2n Switch Matrix R
Fixed Gain +2 Voltage Output Amplifier A high open-loop gain operational amplifier buffers the resistor string with a stable, fixed gain of +2. The voltage output will settle within 13 s. The output is short circuit protected and can regulate an output load of 2V into 2k within 2mV at 25C. While the reference input will accept a voltage from rail-to-rail, the linear input voltage range is constrained by the output swing of the fixed +2 closed-loop gain amplifier. Full scale output swing is achieved with an external reference of approximately 1/2 VDD. The reference voltage must be positive because the XRD54L08/L10/L12 DAC is non-inverting. Serial Daisy-Chainable Digital Interface The three wire serial interface includes a DOUT to enable daisy-chaining of several DACs. This minimizes pin count necessary of digital asics or controllers to address multiple DACS. The serial interface is designed for CMOS logic levels. Timing is shown in Figure 2. The binary coding table (Table 1) shows the DAC transfer function. A power on reset circuit forces the DAC to reset to all "0"s on power up. APPLICATION NOTES Serial Interface The XRD54L08/L10/L12 family has a three wire serial interface that is compatible with Microwiret, SPIt and QSPIt standards. Typical configurations are shown in Figure 4 and Figure 5. Maximum serial port clock rate is limited by the minimum pulse width of tCH and tCL. Feedthrough noise from the serial port to the analog output (VOUT) is minimized by lowering the frequency of the serial port and holding the digital edges to >5ns.
+ R VDD
VOUT
AGND
VDD
CS SCLK SDIN
Shift Register Power On Reset
DOUT
Figure 3. XRD54L08/L10/L12 DAC Architecture The resistor string architecture provides a non-inverted output voltage (VOUT) of the reference input (VREFIN) for single supply operation while maintaining a constant input resistance. Unlike inverted R-2R architectures the reference input resistance will remain constant independent of code. This greatly simplifies the analog driving source requirements for the reference voltage and minimizes distortion. Similarly input capacitance varies only approximately 4pF over all codes.
Rev. 1.30 7
XRD54L08/L10/L12
+5V MP5010 1.25V VREFIN SK Microwiret Port SCLK XRD54L12 SO SDIN VOUT 0-2.5V
I/O
CS GND VDD
0.1mF
+3V
Figure 4. Typical Microwiret Application Circuit
+5V MP5010 1.25V VREFIN SK SPI t Port SCLK XRD54L10 MOSI SDIN VOUT 0-2.5V
I/O
CS GND VDD
0.1mF
+3V
Figure 5. Typical SPIt Application Circuit
Rev. 1.30 8
XRD54L08/L10/L12
DAC
n
SDIN
MSB
X
X
X
X
DOUT
Figure 6. Shift Register Format The DACs are programmed by a 16 bit word of serial data. The format of the serial input register is shown in Figure 6. The leading 4 bits are not used to update the DAC. If the DAC is not daisy-chained then only a 12 bit serial word is needed to program the DAC. The next 8, 10 or 12 bits after the 4 leading bits are data bits. The XRD54L08's first 8 bits are valid data and the trailing 4 bits must be set to 0. Figure 7 demonstrates the 16 bit digital word for the 8, 10,12 bit DACs.
Leading Unused Bits XXXX XXXX XXXX Data Bits MSB LSB XXXXXXXX XXXXXXXX XXXXXXXX Trailing "0" Bits None 00 0000
-+
ACFT Feedthrough (DAC Code = 0) AC Feedthrough from VREFIN to VOUT is minimized with low impedance grounding as shown in Figure 7. If the DAC data is set to all "0"s then VOUT is a function of the divider between the DAC string impedance and ground impedance. See the Power Supply and Grounding section for recommendations. The typical AC feedthrough for a 1kHz 2Vpp signal with code = 0 is -80dB.
VREFIN XRD54L08/L10/L12 RIN
Part XRD54L12 XRD54L10 XRD54L08
Table 2. 16-Bit Digital Word Register for XRD54L08, XRD54L10, XRD54L12. SCLK should be held low when CS transitions low. Data is clocked in on the rising edge of SCLK when CS is low. SDIN data is held in a 16 bit serial shift register. The DAC is updated with the data bits on the rising edge of CS. When CS is high data is not shifted into the XRD54L08/L10/L12. Daisy-Chaining The digital output port (DOUT) has a 4mA drive for greater fan-out capability when daisy-chaining. DOUT allows cascading of multiple DACs with the same serial data stream. The data at SDIN appears at DOUT after 16 clock cycles plus one clock width (tCH) and a propagation delay (tDO). DOUT remains in the state of the last data bit when CS is high. DOUT changes on the falling edge of SCLK when CS is low. Any number of DACs can be connected in this way by connecting DOUT of one DAC to SDIN of the next DAC.
Rev. 1.30 9
GND
VOUT
RGND
Analog GND
Figure 7. ACFT Feedthrough Equivalent Circuit, DAC Code =0 Compatible with MAX515 & MAX539 The XRD54L08/L10/L12 family of DACs are functionally campatible with the MAX515 & MAX539 while providing significant improvements. The XRD54L08/L10/L12 DACs have lower power, faster serial ports, and a constant reference impedance to minimize the reference driving requirements and maximize system linearity while
XRD54L08/L10/L12
operating from a 3V supply versus 5V for the MA515 and MAX539. The DOUT port also has 4mA driving capability for greater fan-out when daisy-chaning to other digital inputs. Monotonicity The XRD54L08/L10/L12 family of DACs are monotonic over the entire temperature range. Micro-Power Operation The XRD54L08/L10/L12 are the lowest power DACs in their class. The quiescent current rating does not include the reference ladder current. Power can be saved when the part is not in use by setting the DAC code to all "0"s assuming the output load is referenced to ground. This minimizes the DAC output load current. An analog switch placed in series with the reference ladder can toggle the reference voltage off when the circuit is inactive to minimize power consumption. PERFORMANCE CHARACTERISTICS
0.04
Power Supply and Grounding Best parametric results are obtained by powering the XRD54L08/L10/L12 family of DACs from an analog +3V power supply and analog ground. Digital power supplies and grounds should be separated or connected to the analog supplies and grounds only at the low-impedance power-supply source. This is best accomplished on a multilayer PCB with dedicated planes to ground and power. The DACs should be locally bypassed with both 0.1 F and 2.2 F capacitors mounted as close as possible to the power supply pin (VDD). Surface mount ceramic capacitors are recommended for low impedance, wide band power supply bypass. If only one +3V power supply is available for both analog and digital circuity isolate the analog power supply to the XRD54L08/L10/L12 DAC with an inductor or ferrite bead before the local bypass capacitors.
--0.04 LSB --0.12 --0.20
0
64
128 CODE
192
255
Figure 8. XRD54L08 INL (For XRD54L10 and XRD54L12, Scale Axes Accordingly)
0.10
0.06 LSB
0.02 0 --0.02
--0.06
0
64
128 CODE
192
255
Figure 9. XRD54L08 DNL (For XRD54L10 and XRD54L12, Scale Axes Accordingly)
Rev. 1.30 10
XRD54L08/L10/L12
Figure 10. Output Source Current vs. Output Voltage
Figure 11. Output Sink Current vs. Output Voltage
16
I (mA)
2mA/div
0 --4 3 .5V/div Vout (V) 0
Figure 12. Output Sink and Source Current vs. Output Volatge
Rev. 1.30 11
XRD54L08/L10/L12
Figure 13. Voltage Output Settling Time (ts), VDD = 5V, VREFIN = 1V, No Load
40 38 36 34 32 Idd ( uA) 30 28 26 24 22 20 --40 --20 0 20 40 Temp ( C ) 60 85 100
Figure 14. IDD vs. Temperature
Rev. 1.30 12
XRD54L08/L10/L12
8 7 6 Gain (dB) 5 4 3 2 1 0 -1 -2 10 100 Frequency (KHz) 1000
Figure 15. Closed Loop Gain vs. Frequency
0 -20 -40 Phase () -60 -80 -100 -120 10 100 Frequency (KHz) 1000
Figure 16. Closed Loop Phase vs. Frequency
Microwiret
is a trademark of National Semiconductor Corproation.
SPIt and QSPIt are trademarks of Motorola Corporation.
Rev. 1.30 13
XRD54L08/L10/L12
8 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP)
Rev. 2.00
8 1 D A L
5 4
E1 E A2 A1
Seating Plane
a
eA eB
C
B
e
B1
INCHES SYMBOL A A1 A2 B B1 C D E E1 e eA eB L MIN 0.145 0.015 0.115 0.014 0.030 0.008 0.348 0.300 0.240 MAX 0.210 0.070 0.195 0.024 0.070 0.014 0.430 0.325 0.280
MILLIMETERS MIN 3.68 0.38 2.92 0.36 0.76 0.20 8.84 7.62 6.10 MAX 5.33 1.78 4.95 0.56 1.78 0.38 10.92 8.26 7.11
0.100 BSC 0.300 BSC 0.310 0.115 0 0.430 0.160 15
2.54 BSC 7.62 BSC 7.87 2.92 0 10.92 4.06 15
a
Note: The control dimension is the inch column
Rev. 1.30 14
XRD54L08/L10/L12
8 LEAD SMALL OUTLINE (150 MIL JEDEC SOIC)
Rev. 1.00
D
8
5 4
E
H
A1 Seating Plane e B
C A
a
L
INCHES SYMBOL A A1 B C D E e H L MIN 0.053 0.004 0.013 0.007 0.189 0.150 0.228 0.016 0 MAX 0.069 0.010 0.020 0.010 0.197 0.157 0.244 0.050 8
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.40 0 MAX 1.75 0.25 0.51 0.25 5.00 4.00 6.20 1.27 8
0.050 BSC
1.27 BSC
a
Note: The control dimension is the millimeter column
Rev. 1.30 15
XRD54L08/L10/L12
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. All trademarks and registered trademarks are property of their respective owners. Copyright 2000 EXAR Corporation Datasheet May 2000 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 1.30 16

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